What is interconnect modeling in VLSI?

Building an IC chip (about the size of a fingernail) is like building a multi-storey building. The first floor contains about a billion semiconductor transistors (referred to as "devices"), and the upper floors contain the metal wires that interconnect the terminals of the "devices". These metal wires are extremely narrow, and there is a maze of these criss-crossing multi-layered metal wires in an IC chip, interconnecting the transistor "device" terminals on the first floor (they drop down from an upper layer to a lower layer using "vias").

There is a lot of parasitic (ie. unwanted) capacitance (C), resistance (R) and inductance (L) in/among these cross-crossing interconnect wires and vias. These parasitic C, R and L degrade the characteristics of the IC chip.

"Interconnect modeling" deals with the modeling of these C, R and L so that they can be accurately considered in predicting/simulating the overall circuit behavior. "Device modeling" on the other hand deals with modeling the behavior of the transistor devices on the first floor.