Microprocessor of 8257 dma controller

8527 DMA controller

The 8527 controller has four independent channels each of which contains an address register and a counter. The counter decrements as each byte transfer occurs, and forces termination of the DMA operation after the last transfer. The controller increments the address register after each operation, so that successive data transfers are made at contiguous ascending addresses.

The arbiter resolves conflicts among the channels for access to memory. Two methods have been used in this chip to make the chip useful in a variety of different applications. In one mode the channels have a fixed priority and conflicts are resolved according to the priority, for example, Channel 0 has highest priority and Channel 3 lowest. The second mode is a rotating priority scheme in which priority rankings are the four cycle shifts of 0-1-2-3, when a channel is granted access to the bus the priority ranking shifts cyclically to place the channel in the lowest priority position for the next arbitration cycle.

Structure of the 8527 DMA controller

The chip has four signals associated with the READ and WRITE operation. MEM READ L and MEM WRITE L are signals produced by DMA controller to exercise memory. The two signals I/O READ L and I/O WRITE L are bidirectional, they are inputs from the microprocessor when the microprocessor sends commands to the 8257 and reads back the 8257 status. During the I/O operation these signals are output from the 8257 and are functionally opposite to the memory signals. The 8257 takes control of the bus by exercising HALT (HRQ) and receives back the "go-ahead" signal on HALT ACKNOWLEDGE (HLDA).

Two signals produced by the DMA controller can be used by the I/O port to assist in controlling the transfer process. One signal TC--terminal count--is asserted during the last cycle of a DMA block. This can be used to describe a DMA mode on an I/O port or to reset the port's internal state to indicate the end of a transfer. The second--MARK--is inserted when the remaining count on a channel became a multiple of 128--providing a convenient timing signal for an external device.

Block Diagram

Pin Configuration

Three Transaction Methods for Peripheral iOS:

• Programmed iOS (like 8255 port used without handshake and Intr signals)

• Interrupt Driven iOS (like 8255 port used without handshake and Inter signals)

• DMA Transactions using a DMAC

Direct Memory Access Control (Peripheral Transactions Server) iOS

· Controller or server sends hold request for processor to grant on acknowledgement, the access to address and data buses, IORD, IOWR, MEMRD, MEMWR and IO buses.

· Once programmed for address of RAM block for transfer and for data counts of IO transactions with RAM, interrupts only at the end of a block transaction or last transaction.

8257 Four Channel DMAC Features:

· Four channels,

· Priority Resolution support,

· TC output and Mark output (after 126 bytes transfer) for interrupts to processor for attention,

· Auto-load on TC mode support for repeat transactions without reprogramming TC and MAR and mode,

· TTL level inputs/outputs compatible with INTEL families.