What is the Difference between verilog and vhdl language?

C is a high level language that is compiled into machine language for specific system.

The system implements some sort of state machine that can process the compiled machine language.

In VHDL you have to design the statemachine itself. Furthermore VHDL is compiled into logic primitives that could be built by logic gates which itself could be realized with transistors.

C is a programming language.

VHDL is a hardware description language.