What is VHDL program for carry look ahead adder?

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY cldf IS

PORT

( a : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

ci : IN STD_LOGIC;

sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

co : OUT STD_LOGI );

END cldf;

ARCHITECTURE df OF cldf IS

SIGNAL h_sum : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL g : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL p : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL cin : STD_LOGIC_VECTOR(3 DOWNTO 1);

BEGIN

h_sum <= a XOR b;

g <= a AND b;

p <= a OR b;

PROCESS (g,p,cin)

BEGIN

cin(1) <= g(0) OR (p(0) AND ci);

inst: FOR i IN 1 TO 2 LOOP

cin(i+1) <= g(i) OR (p(i) AND cin(i));

END LOOP;

co <= g(3) OR (p(3) AND cin(3));

END PROCESS;

sum(0) <= h_sum(0) XOR ci;

sum(3 DOWNTO 1) <= h_sum(3 DOWNTO 1) XOR cin(3 DOWNTO 1);

END df;