What is the VHDL code to implement XOR gate in behavioral model?

Below code can implement OR gate in VHDL.

The code is written in behavioral model.

Library ieee;

use ieee.std_logic_1164.all;

Entity gates is

port (a,b : in std_logic; c : out std_logic);

end gates ;

architecture and1 of gates is

begin

process(a,b)

Begin

If (a=1 or b=1) then

C<='1';

Else

C<= '0';

End if;

End process;

End and1;