What is prefetch queue in 8086?

To speed up the program execution, the B.I.U fetches six instructions byte ahead of time from memory and stores in FIFO registers called "queue". Since EU and B.I.U are independent, the B.I.U fetches additional instruction, while EU decodes and executes a previously fetched instruction.

When the execution unit is ready for its next instruction, it simply reads the instruction from the queue. The main point here is that, fetching of the next instruction is overlapped with the execution of current instruction. This is called pipe lining

pipe lining saves time required for executing instructions. For example, if a multiplication operation is to be performed with its operands and registers, the microprocessor takes 100 clock-cycles, however, without pipe lining and with pipe lining, the number of clock cycles required to multiply two operands get relatively reduced. There are many instructions in 8086 microprocessor that require huge number of clock cycles. Thus, the prefetch queue becomes a circular part in enhancing the performance of the system.