How can I program 4 x 16 decoder in VHDL?

There are many different optional codes. Here are brought three of them.



1st - 2:4 decoder using "enable" :

entity DECODER is
port (A, B, Enable : in std_logic ;
Out : out std_logic_vector(3 downto 0)
);
end DECODER;


architecture ARC.DECODER of DECODER is
begin
Out(0) <= Enable or (not A nand not B);
Out(1) <= Enable or (A nand not B);
Out(2) <= Enable or (not A nand B);
Out(3) <= Enable or (A nand B);
end ARC.DECODER;



2nd - 2:4 decoder using "select" and "with" (case) :

entity DECODER is
port ( SEL : in std_logic_vector(1 downto 0);
outlet : out std_logic_vector(3 downto 0)
);
end DECODER;


architecture ARC.DECODER of DECODER is
begin
with SEL select
outlet <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when "11",
"0000" when others;
end ARC.DECODER;



3rd - 2:4 decoder using "signal", "component" and "map" :

entity DECODER is
Port (A,B : in STD_LOGIC ;
F0,F1,F2,F3 : out STD_LOGIC );
end entity DECODER;


architecture ARC.DECODER of DECODER is


signal A_sig, B_sig : STD_LOGIC;


component INV
port (In1 : in STD_LOGIC ;
Out1 : out STD_LOGIC );
end component;


component AND_2
port (In1, In2 : in STD_LOGIC ;
Out1 : out STD_LOGIC );
end component;
begin
U1 : INV port map (A, A_sig);
U2 : INV port map (B, B_sig);
U3 : AND2 port map (A_sig, B_sig, F0);
U4 : AND2 port map (A, B_sig, F1);
U5 : AND2 port map (A_sig, B, F2);
U6 : AND2 port map (A, B, F3);


end architecture ARC.DECODER;