What is the difference between fpga implementation and verilog implementation?

Verilog HDL / VHDL is a hardware description language used to implement a hardware on a computer virtually. It means that we can append all the attributes of a hardware to a computer program and verify as to how it works. But there may be differences in its behavior when it is actually implemented physically. For example, there may be an unexpected time delay. So, it is required to verify the design physically. Hence, we dump this Verilog / VHDL code into an FPGA / CPLD and verify the design physically.

In other Words, Verilog HDL / VHDL program is used to verify the design on a computer where as FPGA / CPLD implementation is used to verify the design on an IC.