Which logic family has the highest noise immunity?

Each logic family has a noise margin (also called "noise immunity") specified by the manufacturer.

Manufacturers guarantee that the digital logic will still produce correct results even when some small amount of noise is superimposed on a gate output signal.

The maximum amount of such noise that manufacturers are willing to guarantee is the noise margin.

In order from highest to lowest noise immunity:

high-threshold logic: ???

CMOS has a noise margin of 2.95 volts with a 10 V power supply.

CMOS has a noise margin of 1.45 volts with a 5 V power supply.

CMOS has a noise margin of 0.6 volts with a 3 V power supply.

TTL has a noise margin of 0.3 volts.

integrated injection logic (IIL): ???