What are the types of modeling in VHDL?

VHDL can be written in three different models. They are called

• data flow model
• behavioral model
• structural model

Before attempting a VHDL program, one should know the steps involced in these modeling styles.

Data flow model:

In this model, the input data simply flows into the output. THat is, we will be implementing the relation between input and output terminals directly.

For example,

c < = a and b;

Here, the output c is an ANDing of a and b. We are actually implementing the direct relation between inputs and outputs. That is, c = a + b.

Hence, we need not write any complex conditional statements here in data flow model.

Simply implement the output expression. Thats all.

Here, we are implementing the code at a very basic level i. e. circuit level or gate level.

Behavioral model:

Here, in behavioral model, one needs to code the behavior of the system to be designed. If we consider the same above example, the behavior is that, the output should be one (1) whenever both the inputs are one (1).

we can code it like this:

if (a=1 and b=1) then

c<='1';

else

c<='0';

Or, we can even have the behavior like this:

case s is

when "00"=>c<='0';

when "01"=>c<='0';

when "10"=>c<='0';

when "11"=>c<='1';

We are implementing the LOGIC here. We are least bothered about the circuits that can implement this logic. Hence, it is a system level or logic level modeling style.

Structural modeling:

In structural modeling of VHDL, the concept of components is used. In this model, the system to be designed is considered as a combination of sub structures. These sub structures are called components.

For example, a full adder is a combination of two half adders and an or gate. Hence, the components used for designing a full adder are

• half adder
• OR gate

Initially, these components are mentioned in the architecture of a full adder VHDL program. We call this as component initiation. Then the components are called onto the main program and used. Remember, we are using the functionality of the components in main program but we are not coding them in the main program. The code for the component programs will be present somewhere else in the project. Means, code them once and use them infinite number of times.