What is VHDL program for half adder in structural model?

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity has is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

s : out STD_LOGIC;

c : out STD_LOGIC);

end has;

architecture structural of has is

-- component declaration

component xorg

Port ( p : in STD_LOGIC;

q : in STD_LOGIC;

r : out STD_LOGIC);

end component;

component andg

Port ( x : in STD_LOGIC;

y : in STD_LOGIC;

z : out STD_LOGIC);

end component;

begin

u0:xorg port map (a,b,s);

u1:andg port map (a,b,c);

end structural;