Design 4 input xor gate using 2 input nand gate in verilog hdl?

Its possible to design a 4-i/p xor gate using only 2-i/p nand gates

Although the design turns out to be quite complex and comprises of 21 NAND gates :

F = (A'B+AB')(C'D'+CD) + (A'B'+AB)(C'D+CD')

Above given equation is the o/p equation for the circuit .