What is the vhdl program for 4-to-2 encoder?

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ENTITY pri_enc IS

port(a,b,c,d:in std_logic;m:out std_logic_vector(1 downto 0));

END ENTITY pri_enc;

architecture pr_en of pri_enc is

begin

process(a,b,c)

begin

if a='1' then

s<="00";

elsif b='1' then

s<="01";

elsif c='1' then

s<="10";

else s<="11";

end if;

end process;

end pr_en;