What is VHDL program for 2 to 1 multiplexer?

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux2x1 is

Port ( i : in STD_LOGIC_VECTOR (1 downto 0);

s : in STD_LOGIC;

y : out STD_LOGIC);

end mux2x1;

architecture df of mux2x1 is

begin

with s select

y<= i(0) when '0',

i(1) when '1',

'0' when others;

end df;