What is VHDL program for 8 to 1 multiplexer?

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux8X1 is

Port ( en8 : in STD_LOGIC;

s3 : in STD_LOGIC_VECTOR (2 downto 0);

i : in STD_LOGIC_VECTOR (7 downto 0);

y8 : out STD_LOGIC;

y8l : out STD_LOGIC);

end mux8X1;

architecture Behavioral of mux8X1 is

begin

process(en8,s3,i)

begin

if(en8='0') then y8<='0';y8l<='1';

else

case s3 is

when "000" =>y8<=i(0);y8l<=not i(0);

when "001" =>y8<=i(1);y8l<=not i(1);

when "010" =>y8<=i(2);y8l<=not i(2);

when "011" =>y8<=i(3);y8l<=not i(3);

when "100" =>y8<=i(4);y8l<=not i(4);

when "101" =>y8<=i(5);y8l<=not i(5);

when "110" =>y8<=i(6);y8l<=not i(6);

when "111" =>y8<='i(7);y8l<=not i(7);

when others=>' null';

end case;

end if;

end process;

end Behavioral;