State the functions for ALE and TRAP pins in 8085?

In an 8085, the ALE pin pulses high for about one half clock cycle at the beginning of each machine cycle, approximately near the falling edge of CLK. At the falling edge of ALE, external hardware is expected to strobe the values of AD0-AD7 and hold them as the low order address values A0-A7. Other lines, such as IO/M-, S0, S1, and A8-A15 are also guaranteed valid at the falling edge of ALE, but they do not need to be strobed as they are not multiplexed. (All these lines do change during ALE, at about the 1/3 point depending on clock frequency, so they are considered invalid until the falling edge of ALE.) Following ALE, the AD0-AD7 bus lines become the data bus, D0-D7. This multiplexed scheme saves 8 pins on the chip design. In an 8085, the TRAP pin is a non maskable interrupt with highest priority. It must go high and stay high to be recognized, and it will not be recognized again until it goes low and then high. (Edge and level triggered.)The recognition point is on the falling edge of CLK, one clock cycle before the ALE that follows the last machine cycle of the instruction. When recognized, an internal RST instruction ocurrs, with a vector address of 0024H.