What is VHDL program for full adder in data flow model?

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fadf is

Port ( ain : in STD_LOGIC;

bin : in STD_LOGIC;

cin : in STD_LOGIC;

sum : out STD_LOGIC;

cout : out STD_LOGIC);

end fadf;

architecture df of fadf is

begin

sum<= ain xor bin xor cin;

cout<= (ain and bin) or ( bin and cin) or (ain and cin);

end df;